The Mill CPU Architecture

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The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors, PCBs etc) and their programming such as HDL, C/C++, etc.

The Mill CPU Architecture

Unread postby UCERD.COM » Tue Jun 11, 2013 2:46 pm

Interesting video about a new architecture that has a high amount of ILP. They claim to issue 33 instructions per cycle (per core I guess) using their own variant of hyperblocks. It's designed differently to superscalar/VLIW/SIMD and they call it a Belt Machine Architecture.
They use the metric performance per Watt per dollar. I'm not sure if this is typical/correct. Maybe it's really great or maybe just snake oil, you can decide.


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Re: The Mill CPU Architecture

Unread postby pilav » Wed Feb 26, 2014 1:45 am

@Cheema, theoretically, this seems to be fine. VLIW puts multiple instructions in a single word and this apparently tries to get multiple instructions processed using this belt-machine technique. I’m not sure as to how this could be implemented practically as it’s going to be very complicated. The usability for the user is another question that has to be kept in mind. Unlike VLIW, it’s going to be easy for a used to achieve complete optimization for a loop in this case. Let’s hope and see for the best in the future.
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