On-Chip Memory - The Battle Of On-Chip Memories

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The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors, PCBs etc) and their programming such as HDL, C/C++, etc.

On-Chip Memory - The Battle Of On-Chip Memories

Unread postby Tassadaq Cheema » Tue Aug 13, 2013 3:24 pm

HP has photonic inter-node backplanes coming with an Apollo launch later this year, to speed data transfers between compute, storage and networking nodes in a converged system complex by sending light signals instead of electrical ones
A photonic-integrated fabric architecture might achieve 1TB/min.
Hitachi Data Systems believes it can drive the cost of MLC (2-bit multi-layer cell) flash to parity with high-performance SAS disk drive cost by the end of 2015.
Hitachi Data Systems will launch a 3.2TB flash module within weeks or a low number of months, doubling its current 1.6TB size, and will move to 6.4TB modules in 2014. This is aggressive and will give HDS a huge cost advantage over other flash suppliers.

If Memristor technology is used to build shared storage by HP then we could expect to see an HP Memristor array competing with an HDS super-MLC flash array
Image
Last edited by Tassadaq Cheema on Tue Aug 13, 2013 3:34 pm, edited 2 times in total.
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On-Chip Memory -Silicon oxide chip design could replace flas

Unread postby Tassadaq Cheema » Tue Aug 13, 2013 3:26 pm

A Rice University team led by chemist James Tour has built a 1-kilobit rewritable silicon oxide chip that could surpass the limitations of flash memory in packing density, energy consumption per bit, and switching speed.
Normal operating voltages can repeatedly break and “heal” the channel, which can be read as either a “1” or “0” depending on whether it is broken or intact.
The circuits require only two terminals instead of three, as in most memory chips. These crossbar memories are flexible, resist heat and radiation, and show promise for stacking in three-dimensional arrays. Their ability to hold a pattern when exposed to radiation is now being tested aboard the International Space Station .
The diodes also eliminate crosstalk inherent in crossbar structures by keeping the electronic state on a cell from leaking into adjacent cells, Tour said.

Illustration of crossbar memory chips based on silicon oxide that show potential for next-generation 3D memories for computers and consumer devices (credit: Tour Group/Rice University)
The devices, dubbed “one diode-one resistor” (1D-1R), have proven to be robust. They have a high on/off ratio of about 10,000 to 1, over the equivalent of 10 years of use, with low-energy consumption.
They also have the capability for multibit switching, which would allow higher density information storage than conventional two-state memory systems.
The technique is based on an earlier discovery by the Tour lab: when electricity passes through a layer of silicon oxide, it strips away oxygen molecules and creates a channel of pure metallic-phase silicon that is less than five nanometers wide.
The Boeing Corp. and the Air Force Office of Scientific Research funded the work.

Related Materials:

In situ imaging of the conducting filament in a silicon oxide resistive switch
REFERENCES:
Gunuk Wang et al., High-Performance and Low-Power Rewritable SiOx 1 kbit One Diode–One Resistor Crossbar Memory Array, Advanced Materials, 2013, DOI: 10.1002/adma.201302047
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EDRAM - IBM to Ditch SRAM for Embedded DRAM on Power CPUs

Unread postby Tassadaq Cheema » Tue Aug 13, 2013 4:29 pm

IBM’s line of POWER processors—now at its 7th generation—is based on the Power Architecture instruction set architecture, driven primarily by IBM and Fre-
escale, within the Power.org industrial consortium. The ISA has a RISC architecture and it’s open for licensing. Despite the pervasive nature of the X86 ISA (on which
Intel and AMD processors are based) in the server space, roughly half of the Top 50 supercomputers are based on processors using the Power Architecture (all built by
IBM). Additionally, the Power architecture is available in many specialized chips, including almost all game console processors.
The main characteristics of the Power 7 family of processors are:
• 4, 6 or 8 cores per chip, with execution frequencies exceeding 4 GHz; a more conventional limit is around 3–3.5€GHz—which still puts power consumption over the 200 W bar
• 4-way SMT, resulting in 32-way SMT per processor, with aggressive out of or- der execution
• 32 Mb on chip, embedded DRAM based shared L3 cache, on top of the 64kb/core L1 and 256kb/core L2 cache, tightly coupled with the cores
• Scalability up to 32 sockets, with “near linear” performance scaling claimed by IBM
• Advanced power optimization designs
• Distributive resource management which allows re-allocation of resources (cache and external memory bandwidth) between cores, depending on the application that is being executed Power7 processors stand out—in our opinion—with two design choices: the usage of eDRAM (which we have discussed elsewhere in this chapter) as basis for L3
cache and the advanced power management features. The cores in the Power7 processors support two idle modes:
• nap mode, optimized for wake-up time: clocks are turned off towards the execution units, frequency is reduced, but caches and virtual memory management
tables remain coherent, thus the core can be brought back to full speed quicker
• sleep mode, optimized for power reduction: clocks are fully turned off, caches are purged and voltage reduced to a level where leakage current is substantially
lowered; however, at wake-up still no re-initialization of the core is required The processors also support active energy management, commercially called Energy Scale, consisting of the following technologies:
• DVFS (dynamic voltage and frequency scaling) within the range of − 50% to +10% of the nominal core frequency
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