High Level Synthesis Tools

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The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors, PCBs etc) and their programming such as HDL, C/C++, etc.

High Level Synthesis Tools

Unread postby UCERD.COM » Sat Sep 13, 2014 8:30 pm

Over the past few years, High Level Synthesis (HLS) tools have been developed that add the necessary technologies to become truly production worthy. Initially limited to data path designs, HLS tools have now started to address complete systems, including control logic and complex on-chip, off-chip interconnection. ROCCC 2.0 [1] is a free and open source tool that focuses on FPGA-based code acceleration from a subset of the C language.
ROCCC tries to exploit parallelism within the constraints of the target device, optimize clock cycle time by pipelining, and minimize area. Recently Xilinx acquired AutoESL together with its AutoPilot HLS tool [2]. It takes C, C++, or SystemC as its input and produces device-specific RTL for Xilinx FPGA devices. Xilinx ISE and EDK tool chain are used to convert the generated RTL to the final bitstream. Impulse Accelerated Technologies develops the ImpulseC programming language [3], a commercialization of StreamsC [4]. The Impulse C tools comprise a software-to-hardware compiler that translates individual Impulse C processes to hardware and generates the necessary process-to-process interface logic. Handel-C, developed by Celoxica [5], is based on the syntax of conventional C language. Programs written in Handel-C are implicitly sequential. To exploit benefits of parallelism from the target hardware, HandelC provides parallel constructs such as pipelined communication and parallel sections. Catapult C, designed by Mentor Graphics [6], is a subset of C++. The code that is compiled through Catapult C may be general purpose and result in much different hardware implementations with different timing and resource constraints. The Catapult C environment takes constraints and platform details in order to generate a set of optimal implementations.
Ylichron (now PLDA Italia) developed a source-to-source C to VHDL compiler toolchain targeting system designers called HCE (Hardware Compiling Environment). The HCE toolchain [7] takes ANSI-C language as input, which describes the hardware architecture with some limitations and extensions. The HCE design flow consists of a sequence of steps (see Figure 1), with each step transforming the abstraction level of the algorithm into a lower level description. The HCE first extracts the Control and Data Flow Graph (CDFG) from the application to be synthesized. The CDFGs describe the computational nodes and edges between the nodes. HCE provides different methods to explore the CDFG of the input algorithm and generates the data-path structure. The generated data-path structure contains the user-defined number of computing resources for each computing node type and the number of storage resources (registers). The Allocation and Scheduling step maps the CDFG algorithm onto the computing data-path and produces a Finite State Control Machine. The system refine step uses the appropriate Board Support Package and performs synthesis for the communication network. Finally, the VHDL- RTL generation step produces the VHDL files to be supplied to the proprietary synthesis tools for the targeted FPGA.
[1] “Riverside Optimizing Compiler for Configurable Computing (ROCCC 2.0),” 3,April 2011. [Online].
Available: http://www.jacquardcomputing.com/roccc/
[2] “AutoESL High-Level Synthesis Tool.” [Online].
Available: http://www.xilinx.com/tools/autoesl.htm
[3] “Impulse CoDeveloper Overview,” 3,April 2011.
[Online]. Available: http://www.impulseaccelerated.com/
[4] M. B. Gokhale, J. M. Stone, J. Arnold, and M. Kalinowski, “Stream-oriented fpga computing in the streams-c high level language.” IEEE Computer Society, 2000.
[5] Matthew Bowen, “Handel-C Language Reference Manual,” Embedded Solutions Limited. Version 2.1.
[Online]. Available: http://www.pa.msu.edu/hep/d0/l2/Handel-C/Handel%20C.PDF
[6] , “Catapult C Synthesis Overview,” 3,April 2011.
[Online]. Available: http://www.mentor.com/esl/catapult/overview
[7] PLDA, HCE - Hardware Compiling Environment Reference Manual, July 2010.
[8] “XP4S530-MEM ”MEMO”.”
[Online]. Available: http://www.accelize.com/fpga-compute-ca ... 0-mem.html
[9] Araya-Polo, M.; Cabezas, J.; Hanzich, M.; Pericas, M.;Rubio, F.; Gelado, I.; Shafiq, M.; Morancho, E.; Navarro, N.; Ayguade, E.; Cela, J.M.; Valero, M, “Assessing
Accelerator-Based HPC Reverse Time Migration,” Parallel and Distributed Systems, IEEE Transactions , Jan 2011.
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