Computer Memory Survey and Promising Memories Xtics

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EDRAM - IBM to Ditch SRAM for Embedded DRAM on Power CPUs

Unread postby UCERD.COM » Wed Nov 27, 2013 12:57 pm

IBM’s line of POWER processors—now at its 7th generation—is based on the Power Architecture instruction set architecture, driven primarily by IBM and Fre escale, within the Power.org industrial consortium. The ISA has a RISC architecture and it’s open for licensing. Despite the pervasive nature of the X86 ISA (on which
Intel and AMD processors are based) in the server space, roughly half of the Top 50 supercomputers are based on processors using the Power Architecture (all built by
IBM). Additionally, the Power architecture is available in many specialized chips, including almost all game console processors.
The main characteristics of the Power 7 family of processors are:
• 4, 6 or 8 cores per chip, with execution frequencies exceeding 4 GHz; a more conventional limit is around 3–3.5€GHz—which still puts power consumption over the 200 W bar
• 4-way SMT, resulting in 32-way SMT per processor, with aggressive out of or- der execution
• 32 Mb on chip, embedded DRAM based shared L3 cache, on top of the 64kb/core L1 and 256kb/core L2 cache, tightly coupled with the cores
• Scalability up to 32 sockets, with “near linear” performance scaling claimed by IBM
• Advanced power optimization designs
• Distributive resource management which allows re-allocation of resources (cache and external memory bandwidth) between cores, depending on the application that is being executed Power7 processors stand out—in our opinion—with two design choices: the usage of eDRAM (which we have discussed elsewhere in this chapter) as basis for L3
cache and the advanced power management features. The cores in the Power7 processors support two idle modes:
• nap mode, optimized for wake-up time: clocks are turned off towards the execution units, frequency is reduced, but caches and virtual memory management
tables remain coherent, thus the core can be brought back to full speed quicker
• sleep mode, optimized for power reduction: clocks are fully turned off, caches are purged and voltage reduced to a level where leakage current is substantially
lowered; however, at wake-up still no re-initialization of the core is required The processors also support active energy management, commercially called Energy Scale, consisting of the following technologies:
• DVFS (dynamic voltage and frequency scaling) within the range of − 50% to +10% of the nominal core frequency
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